Die manufactured for use in a die stack must be tested at the wafer level and then potentially retested after the die are singulated to ensure only known good die are used in the stack. Each time an upper die is stacked on top of a lower die that has been tested, the upper die needs to be retested to ensure it has not been damaged during the stacking process. Also, the interconnect between the lower and upper die needs to be tested and determined good. The interconnect between die in a 3D stack is provided by Through Silicon Vias (TSVs), which are vertical signaling paths between the bottom and top surfaces of each die. This testing process is repeated for each additional upper die assembled onto the stack. It is therefore advantageous to have a common test architecture in each die and a common method of accessing the test architecture in each die, independent of the stacked location of the die.